TC2XC2S=TCLK2, TC0XC0S=TCLK0, TC1XC1S=TCLK1
Block Mode Register
| TC0XC0S | External Clock Signal 0 Selection 0 (TCLK0): Signal connected to XC0: TCLK0 2 (TIOA1): Signal connected to XC0: TIOA1 3 (TIOA2): Signal connected to XC0: TIOA2 |
| TC1XC1S | External Clock Signal 1 Selection 0 (TCLK1): Signal connected to XC1: TCLK1 2 (TIOA0): Signal connected to XC1: TIOA0 3 (TIOA2): Signal connected to XC1: TIOA2 |
| TC2XC2S | External Clock Signal 2 Selection 0 (TCLK2): Signal connected to XC2: TCLK2 2 (TIOA1): Signal connected to XC2: TIOA1 3 (TIOA2): Signal connected to XC2: TIOA2 |
| QDEN | Quadrature Decoder ENabled |
| POSEN | POSition ENabled |
| SPEEDEN | SPEED ENabled |
| QDTRANS | Quadrature Decoding TRANSparent |
| EDGPHA | EDGe on PHA count mode |
| INVA | INVerted phA |
| INVB | INVerted phB |
| INVIDX | INVerted InDeX |
| SWAP | SWAP PHA and PHB |
| IDXPHB | InDeX pin is PHB pin |
| FILTER | |
| MAXFILT | MAXimum FILTer |