SRC_DSCR=FETCH_FROM_MEM, DST_DSCR=FETCH_FROM_MEM, DST_INCR=INCREMENTING, SRC_INCR=INCREMENTING, FC=MEM2MEM_DMA_FC
DMAC Channel Control B Register (ch_num = 5)
| SRC_DSCR | Source Address Descriptor 0 (FETCH_FROM_MEM): Source address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the source. |
| DST_DSCR | Destination Address Descriptor 0 (FETCH_FROM_MEM): Destination address is updated when the descriptor is fetched from the memory. 1 (FETCH_DISABLE): Buffer Descriptor Fetch operation is disabled for the destination. |
| FC | Flow Control 0 (MEM2MEM_DMA_FC): Memory-to-Memory Transfer DMAC is flow controller 1 (MEM2PER_DMA_FC): Memory-to-Peripheral Transfer DMAC is flow controller 2 (PER2MEM_DMA_FC): Peripheral-to-Memory Transfer DMAC is flow controller 3 (PER2PER_DMA_FC): Peripheral-to-Peripheral Transfer DMAC is flow controller |
| SRC_INCR | Incrementing, Decrementing or Fixed Address for the Source 0 (INCREMENTING): The source address is incremented 1 (DECREMENTING): The source address is decremented 2 (FIXED): The source address remains unchanged |
| DST_INCR | Incrementing, Decrementing or Fixed Address for the Destination 0 (INCREMENTING): The destination address is incremented 1 (DECREMENTING): The destination address is decremented 2 (FIXED): The destination address remains unchanged |
| IEN | Interrupt Enable Not |