Atmel /ATSAM3X8H /EMAC /NCFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as NCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPD)SPD 0 (FD)FD 0 (JFRAME)JFRAME 0 (CAF)CAF 0 (NBC)NBC 0 (MTI)MTI 0 (UNI)UNI 0 (BIG)BIG 0 (MCK_8)CLK0 (RTY)RTY 0 (PAE)PAE 0 (OFFSET_0)RBOF 0 (RLCE)RLCE 0 (DRFCS)DRFCS 0 (EFRHD)EFRHD 0 (IRXFCS)IRXFCS

CLK=MCK_8, RBOF=OFFSET_0

Description

Network Configuration Register

Fields

SPD

Speed

FD

Full Duplex

JFRAME

Jumbo Frames

CAF

Copy All Frames

NBC

No Broadcast

MTI

Multicast Hash Enable

UNI

Unicast Hash Enable

BIG

Receive 1536 bytes frames

CLK

MDC clock divider

0 (MCK_8): MCK divided by 8 (MCK up to 20 MHz).

1 (MCK_16): MCK divided by 16 (MCK up to 40 MHz).

2 (MCK_32): MCK divided by 32 (MCK up to 80 MHz).

3 (MCK_64): MCK divided by 64 (MCK up to 160 MHz).

RTY

Retry test

PAE

Pause Enable

RBOF

Receive Buffer Offset

0 (OFFSET_0): No offset from start of receive buffer.

1 (OFFSET_1): One-byte offset from start of receive buffer.

2 (OFFSET_2): Two-byte offset from start of receive buffer.

3 (OFFSET_3): Three-byte offset from start of receive buffer.

RLCE

Receive Length field Checking Enable

DRFCS

Discard Receive FCS

EFRHD
IRXFCS

Ignore RX FCS

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