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Atmel /ATSAM3X8H /PWM /IDR1

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Interpret as IDR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHID0)CHID0 0 (CHID1)CHID1 0 (CHID2)CHID2 0 (CHID3)CHID3 0 (CHID4)CHID4 0 (CHID5)CHID5 0 (CHID6)CHID6 0 (CHID7)CHID7 0 (FCHID0)FCHID0 0 (FCHID1)FCHID1 0 (FCHID2)FCHID2 0 (FCHID3)FCHID3 0 (FCHID4)FCHID4 0 (FCHID5)FCHID5 0 (FCHID6)FCHID6 0 (FCHID7)FCHID7

Description

PWM Interrupt Disable Register 1

Fields

CHID0

Counter Event on Channel 0 Interrupt Disable
CHID1

Counter Event on Channel 1 Interrupt Disable
CHID2

Counter Event on Channel 2 Interrupt Disable
CHID3

Counter Event on Channel 3 Interrupt Disable
CHID4

Counter Event on Channel 4 Interrupt Disable
CHID5

Counter Event on Channel 5 Interrupt Disable
CHID6

Counter Event on Channel 6 Interrupt Disable
CHID7

Counter Event on Channel 7 Interrupt Disable
FCHID0

Fault Protection Trigger on Channel 0 Interrupt Disable
FCHID1

Fault Protection Trigger on Channel 1 Interrupt Disable
FCHID2

Fault Protection Trigger on Channel 2 Interrupt Disable
FCHID3

Fault Protection Trigger on Channel 3 Interrupt Disable
FCHID4

Fault Protection Trigger on Channel 4 Interrupt Disable
FCHID5

Fault Protection Trigger on Channel 5 Interrupt Disable
FCHID6

Fault Protection Trigger on Channel 6 Interrupt Disable
FCHID7

Fault Protection Trigger on Channel 7 Interrupt Disable

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data