CKG=CONTINUOUS, START=CONTINUOUS, CKS=MCK, CKO=NONE
Receive Clock Mode Register
| CKS | Receive Clock Selection 0 (MCK): Divided Clock 1 (TK): TK Clock signal 2 (RK): RK pin |
| CKO | Receive Clock Output Mode Selection 0 (NONE): None, RK pin is an input 1 (CONTINUOUS): Continuous Receive Clock, RK pin is an output 2 (TRANSFER): Receive Clock only during data transfers, RK pin is an output |
| CKI | Receive Clock Inversion |
| CKG | Receive Clock Gating Selection 0 (CONTINUOUS): None 1 (EN_RF_LOW): Receive Clock enabled only if RF Low 2 (EN_RF_HIGH): Receive Clock enabled only if RF High |
| START | Receive Start Selection 0 (CONTINUOUS): Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 1 (TRANSMIT): Transmit start 2 (RF_LOW): Detection of a low level on RF signal 3 (RF_HIGH): Detection of a high level on RF signal 4 (RF_FALLING): Detection of a falling edge on RF signal 5 (RF_RISING): Detection of a rising edge on RF signal 6 (RF_LEVEL): Detection of any level change on RF signal 7 (RF_EDGE): Detection of any edge on RF signal 8 (CMP_0): Compare 0 |
| STOP | Receive Stop Selection |
| STTDLY | Receive Start Delay |
| PERIOD | Receive Period Divider Selection |