SETTLING=AST3, USEQ=NUM_ORDER, ANACH=NONE, STARTUP=SUT0, TRGEN=DIS, FREERUN=OFF, SLEEP=NORMAL, FWUP=OFF, TRGSEL=ADC_TRIG0
Mode Register
| TRGEN | Trigger Enable 0 (DIS): Hardware triggers are disabled. Starting a conversion is only possible by software. 1 (EN): Hardware trigger selected by TRGSEL field is enabled. |
| TRGSEL | Trigger Selection 0 (ADC_TRIG0): External trigger 1 (ADC_TRIG1): TIO Output of the Timer Counter Channel 0 2 (ADC_TRIG2): TIO Output of the Timer Counter Channel 1 3 (ADC_TRIG3): TIO Output of the Timer Counter Channel 2 4 (ADC_TRIG4): PWM Event Line 0 5 (ADC_TRIG5): PWM Event Line 1 |
| SLEEP | Sleep Mode 0 (NORMAL): Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. 1 (SLEEP): Sleep Mode: The wake-up time can be modified by programming FWUP bit. |
| FWUP | Fast Wake Up 0 (OFF): If SLEEP is 1, then both ADC core and reference voltage circuitry are OFF between conversions 1 (ON): If SLEEP is 1, then Fast Wake-up Sleep mode: The voltage reference is ON between conversions and ADC core is OFF |
| FREERUN | Free Run Mode 0 (OFF): Normal Mode 1 (ON): Free Run Mode: Never wait for any trigger. |
| PRESCAL | Prescaler Rate Selection |
| STARTUP | Startup Time 0 (SUT0): 0 periods of ADCCLK 1 (SUT8): 8 periods of ADCCLK 2 (SUT16): 16 periods of ADCCLK 3 (SUT24): 24 periods of ADCCLK 4 (SUT64): 64 periods of ADCCLK 5 (SUT80): 80 periods of ADCCLK 6 (SUT96): 96 periods of ADCCLK 7 (SUT112): 112 periods of ADCCLK 8 (SUT512): 512 periods of ADCCLK 9 (SUT576): 576 periods of ADCCLK 10 (SUT640): 640 periods of ADCCLK 11 (SUT704): 704 periods of ADCCLK 12 (SUT768): 768 periods of ADCCLK 13 (SUT832): 832 periods of ADCCLK 14 (SUT896): 896 periods of ADCCLK 15 (SUT960): 960 periods of ADCCLK |
| SETTLING | Analog Settling Time 0 (AST3): 3 periods of ADCCLK 1 (AST5): 5 periods of ADCCLK 2 (AST9): 9 periods of ADCCLK 3 (AST17): 17 periods of ADCCLK |
| ANACH | Analog Change 0 (NONE): No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels. 1 (ALLOWED): Allows different analog settings for each channel. See ADC_CGR and ADC_COR registers. |
| TRACKTIM | Tracking Time |
| TRANSFER | Hold Time |
| USEQ | Use Sequence Enable 0 (NUM_ORDER): Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 1 (REG_ORDER): User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert the same channel several times. |