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Atmel /ATSAM4S4B /DACC /ACR

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Interpret as ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IBCTLCH0 0IBCTLCH1 0IBCTLDACCORE

Description

Analog Current Register

Fields

IBCTLCH0

Analog Output Current Control
IBCTLCH1

Analog Output Current Control
IBCTLDACCORE

Bias Current Control for DAC Core

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data