Atmel /ATSAM4S4B /HSMCI /SR

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Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CMDRDY)CMDRDY 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (BLKE)BLKE 0 (DTIP)DTIP 0 (NOTBUSY)NOTBUSY 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (SDIOIRQA)SDIOIRQA 0 (SDIOWAIT)SDIOWAIT 0 (CSRCV)CSRCV 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE 0 (RINDE)RINDE 0 (RDIRE)RDIRE 0 (RCRCE)RCRCE 0 (RENDE)RENDE 0 (RTOE)RTOE 0 (DCRCE)DCRCE 0 (DTOE)DTOE 0 (CSTOE)CSTOE 0 (FIFOEMPTY)FIFOEMPTY 0 (XFRDONE)XFRDONE 0 (ACKRCV)ACKRCV 0 (ACKRCVE)ACKRCVE 0 (OVRE)OVRE 0 (UNRE)UNRE

Description

Status Register

Fields

CMDRDY

Command Ready (cleared by writing in HSMCI_CMDR)

RXRDY

Receiver Ready (cleared by reading HSMCI_RDR)

TXRDY

Transmit Ready (cleared by writing in HSMCI_TDR)

BLKE

Data Block Ended (cleared on read)

DTIP

Data Transfer in Progress (cleared at the end of CRC16 calculation)

NOTBUSY

HSMCI Not Busy

ENDRX

End of RX Buffer (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))

ENDTX

End of TX Buffer (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))

SDIOIRQA

SDIO Interrupt for Slot A (cleared on read)

SDIOWAIT

SDIO Read Wait Operation Status

CSRCV

CE-ATA Completion Signal Received (cleared on read)

RXBUFF

RX Buffer Full (cleared by writing HSMCI_RCR or HSMCI_RNCR(1))

TXBUFE

TX Buffer Empty (cleared by writing HSMCI_TCR or HSMCI_TNCR(1))

RINDE

Response Index Error (cleared by writing in HSMCI_CMDR)

RDIRE

Response Direction Error (cleared by writing in HSMCI_CMDR)

RCRCE

Response CRC Error (cleared by writing in HSMCI_CMDR)

RENDE

Response End Bit Error (cleared by writing in HSMCI_CMDR)

RTOE

Response Time-out Error (cleared by writing in HSMCI_CMDR)

DCRCE

Data CRC Error (cleared on read)

DTOE

Data Time-out Error (cleared on read)

CSTOE

Completion Signal Time-out Error (cleared on read)

FIFOEMPTY

FIFO empty flag

XFRDONE

Transfer Done flag

ACKRCV

Boot Operation Acknowledge Received (cleared on read)

ACKRCVE

Boot Operation Acknowledge Error (cleared on read)

OVRE

Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)

UNRE

Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)

Links

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