Atmel /ATSAM4S4B /PWM /CLK

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Interpret as CLK

DIVB=CLKB_POFF, PREA=CLK, DIVA=CLKA_POFF, PREB=CLK

Description

PWM Clock Register

Fields

DIVA	CLKA Divide Factor 0 (CLKA_POFF): CLKA clock is turned off 1 (PREA): CLKA clock is clock selected by PREA
PREA	CLKA Source Clock Selection 0 (CLK): Peripheral clock 1 (CLK_DIV2): Peripheral clock/2 2 (CLK_DIV4): Peripheral clock/4 3 (CLK_DIV8): Peripheral clock/8 4 (CLK_DIV16): Peripheral clock/16 5 (CLK_DIV32): Peripheral clock/32 6 (CLK_DIV64): Peripheral clock/64 7 (CLK_DIV128): Peripheral clock/128 8 (CLK_DIV256): Peripheral clock/256 9 (CLK_DIV512): Peripheral clock/512 10 (CLK_DIV1024): Peripheral clock/1024
DIVB	CLKB Divide Factor 0 (CLKB_POFF): CLKB clock is turned off 1 (PREB): CLKB clock is clock selected by PREB
PREB	CLKB Source Clock Selection 0 (CLK): Peripheral clock 1 (CLK_DIV2): Peripheral clock/2 2 (CLK_DIV4): Peripheral clock/4 3 (CLK_DIV8): Peripheral clock/8 4 (CLK_DIV16): Peripheral clock/16 5 (CLK_DIV32): Peripheral clock/32 6 (CLK_DIV64): Peripheral clock/64 7 (CLK_DIV128): Peripheral clock/128 8 (CLK_DIV256): Peripheral clock/256 9 (CLK_DIV512): Peripheral clock/512 10 (CLK_DIV1024): Peripheral clock/1024

Links

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