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Atmel /ATSAM4S4B /PWM /DT2

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Interpret as DT2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTH0DTL

Description

PWM Channel Dead Time Register (ch_num = 2)

Fields

DTH

Dead-Time Value for PWMHx Output
DTL

Dead-Time Value for PWMLx Output

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data