Regviz

Atmel /ATSAM4S4B /PWM /IMR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IMR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J20/PWM0/IMR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CHID0)CHID0 0 (CHID1)CHID1 0 (CHID2)CHID2 0 (CHID3)CHID3 0 (FCHID0)FCHID0 0 (FCHID1)FCHID1 0 (FCHID2)FCHID2 0 (FCHID3)FCHID3

Description

PWM Interrupt Mask Register 1

Fields

CHID0

Counter Event on Channel 0 Interrupt Mask
CHID1

Counter Event on Channel 1 Interrupt Mask
CHID2

Counter Event on Channel 2 Interrupt Mask
CHID3

Counter Event on Channel 3 Interrupt Mask
FCHID0

Fault Protection Trigger on Channel 0 Interrupt Mask
FCHID1

Fault Protection Trigger on Channel 1 Interrupt Mask
FCHID2

Fault Protection Trigger on Channel 2 Interrupt Mask
FCHID3

Fault Protection Trigger on Channel 3 Interrupt Mask

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data