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Atmel /ATSAM4S4B /TC0 /BMR

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Interpret as BMR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TCLK0)TC0XC0S 0 (TCLK1)TC1XC1S 0 (TCLK2)TC2XC2S 0 (QDEN)QDEN 0 (POSEN)POSEN 0 (SPEEDEN)SPEEDEN 0 (QDTRANS)QDTRANS 0 (EDGPHA)EDGPHA 0 (INVA)INVA 0 (INVB)INVB 0 (INVIDX)INVIDX 0 (SWAP)SWAP 0 (IDXPHB)IDXPHB 0MAXFILT

TC2XC2S=TCLK2, TC0XC0S=TCLK0, TC1XC1S=TCLK1

Description

Block Mode Register

Fields

TC0XC0S

External Clock Signal 0 Selection

0 (TCLK0): Signal connected to XC0: TCLK0

2 (TIOA1): Signal connected to XC0: TIOA1

3 (TIOA2): Signal connected to XC0: TIOA2
TC1XC1S

External Clock Signal 1 Selection

0 (TCLK1): Signal connected to XC1: TCLK1

2 (TIOA0): Signal connected to XC1: TIOA0

3 (TIOA2): Signal connected to XC1: TIOA2
TC2XC2S

External Clock Signal 2 Selection

0 (TCLK2): Signal connected to XC2: TCLK2

2 (TIOA0): Signal connected to XC2: TIOA0

3 (TIOA1): Signal connected to XC2: TIOA1
QDEN

Quadrature Decoder Enabled
POSEN

Position Enabled
SPEEDEN

Speed Enabled
QDTRANS

Quadrature Decoding Transparent
EDGPHA

Edge on PHA Count Mode
INVA

Inverted PHA
INVB

Inverted PHB
INVIDX

Inverted Index
SWAP

Swap PHA and PHB
IDXPHB

Index Pin is PHB Pin
MAXFILT

Maximum Filter

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data