Atmel /ATSAM4S4B /TWI1 /IDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCL_WS)SCL_WS 0 (EOSACC)EOSACC 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE

Description

Interrupt Disable Register

Fields

TXCOMP

Transmission Completed Interrupt Disable

RXRDY

Receive Holding Register Ready Interrupt Disable

TXRDY

Transmit Holding Register Ready Interrupt Disable

SVACC

Slave Access Interrupt Disable

GACC

General Call Access Interrupt Disable

OVRE

Overrun Error Interrupt Disable

NACK

Not Acknowledge Interrupt Disable

ARBLST

Arbitration Lost Interrupt Disable

SCL_WS

Clock Wait State Interrupt Disable

EOSACC

End Of Slave Access Interrupt Disable

ENDRX

End of Receive Buffer Interrupt Disable

ENDTX

End of Transmit Buffer Interrupt Disable

RXBUFF

Receive Buffer Full Interrupt Disable

TXBUFE

Transmit Buffer Empty Interrupt Disable

Links

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