Atmel /ATSAM4S4B /TWI1 /IER

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Interpret as IER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCL_WS)SCL_WS 0 (EOSACC)EOSACC 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE

Description

Interrupt Enable Register

Fields

TXCOMP

Transmission Completed Interrupt Enable

RXRDY

Receive Holding Register Ready Interrupt Enable

TXRDY

Transmit Holding Register Ready Interrupt Enable

SVACC

Slave Access Interrupt Enable

GACC

General Call Access Interrupt Enable

OVRE

Overrun Error Interrupt Enable

NACK

Not Acknowledge Interrupt Enable

ARBLST

Arbitration Lost Interrupt Enable

SCL_WS

Clock Wait State Interrupt Enable

EOSACC

End Of Slave Access Interrupt Enable

ENDRX

End of Receive Buffer Interrupt Enable

ENDTX

End of Transmit Buffer Interrupt Enable

RXBUFF

Receive Buffer Full Interrupt Enable

TXBUFE

Transmit Buffer Empty Interrupt Enable

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