Atmel /ATSAM4S4B /TWI1 /IMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCL_WS)SCL_WS 0 (EOSACC)EOSACC 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE

Description

Interrupt Mask Register

Fields

TXCOMP

Transmission Completed Interrupt Mask

RXRDY

Receive Holding Register Ready Interrupt Mask

TXRDY

Transmit Holding Register Ready Interrupt Mask

SVACC

Slave Access Interrupt Mask

GACC

General Call Access Interrupt Mask

OVRE

Overrun Error Interrupt Mask

NACK

Not Acknowledge Interrupt Mask

ARBLST

Arbitration Lost Interrupt Mask

SCL_WS

Clock Wait State Interrupt Mask

EOSACC

End Of Slave Access Interrupt Mask

ENDRX

End of Receive Buffer Interrupt Mask

ENDTX

End of Transmit Buffer Interrupt Mask

RXBUFF

Receive Buffer Full Interrupt Mask

TXBUFE

Transmit Buffer Empty Interrupt Mask

Links

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