Atmel /ATSAM4S4B /TWI1 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVREAD)SVREAD 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCLWS)SCLWS 0 (EOSACC)EOSACC 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (RXBUFF)RXBUFF 0 (TXBUFE)TXBUFE

Description

Status Register

Fields

TXCOMP

Transmission Completed (cleared by writing TWI_THR)

RXRDY

Receive Holding Register Ready (cleared by reading TWI_RHR)

TXRDY

Transmit Holding Register Ready (cleared by writing TWI_THR)

SVREAD

Slave Read

SVACC

Slave Access

GACC

General Call Access (cleared on read)

OVRE

Overrun Error (cleared on read)

NACK

Not Acknowledged (cleared on read)

ARBLST

Arbitration Lost (cleared on read)

SCLWS

Clock Wait State

EOSACC

End Of Slave Access (cleared on read)

ENDRX

End of RX buffer (cleared by writing TWI_RCR or TWI_RNCR)

ENDTX

End of TX buffer (cleared by writing TWI_TCR or TWI_TNCR)

RXBUFF

RX Buffer Full (cleared by writing TWI_RCR or TWI_RNCR)

TXBUFE

TX Buffer Empty (cleared by writing TWI_TCR or TWI_TNCR)

Links

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