Regviz

Atmel /ATSAM4S4B /UART1 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Atmel/ATSAM4S4B/UART1/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (OVRE)OVRE 0 (FRAME)FRAME 0 (PARE)PARE 0 (TXEMPTY)TXEMPTY 0 (TXBUFE)TXBUFE 0 (RXBUFF)RXBUFF

Description

Status Register

Fields

RXRDY

Receiver Ready
TXRDY

Transmitter Ready
ENDRX

End of Receiver Transfer
ENDTX

End of Transmitter Transfer
OVRE

Overrun Error
FRAME

Framing Error
PARE

Parity Error
TXEMPTY

Transmitter Empty
TXBUFE

Transmission Buffer Empty
RXBUFF

Receive Buffer Full

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data