Atmel /ATSAM4S4B /USART1 /CSR_SPI_MODE

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Interpret as CSR_SPI_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (ENDRX)ENDRX 0 (ENDTX)ENDTX 0 (OVRE)OVRE 0 (TXEMPTY)TXEMPTY 0 (UNRE)UNRE 0 (TXBUFE)TXBUFE 0 (RXBUFF)RXBUFF

Description

Channel Status Register

Fields

RXRDY

Receiver Ready (cleared by reading US_RHR)

TXRDY

Transmitter Ready (cleared by writing US_THR)

ENDRX

End of RX Buffer (cleared by writing US_RCR or US_RNCR)

ENDTX

End of TX Buffer (cleared by writing US_TCR or US_TNCR)

OVRE

Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)

TXEMPTY

Transmitter Empty (cleared by writing US_THR)

UNRE

Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)

TXBUFE

TX Buffer Empty (cleared by writing US_TCR or US_TNCR)

RXBUFF

RX Buffer Full (cleared by writing US_RCR or US_RNCR)

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