Regviz

Atmel /ATSAM4S4B /WDT /SR

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Interpret as SR

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https://regviz.com/r/Microchip Technology/ATSAMV71J20/WDT/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDUNF)WDUNF 0 (WDERR)WDERR

Description

Status Register

Fields

WDUNF

Watchdog Underflow (cleared on read)
WDERR

Watchdog Error (cleared on read)

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data