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Atmel /ATSAM4S8B /RTT /SR

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Interpret as SR

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https://regviz.com/r/Microchip Technology/ATSAMV71J20/RTT/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALMS)ALMS 0 (RTTINC)RTTINC

Description

Status Register

Fields

ALMS

Real-time Alarm Status (cleared on read)
RTTINC

Prescaler Roll-over Status (cleared on read)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data