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Atmel /ATSAM4S8B /SSC /SR

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Interpret as SR

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https://regviz.com/r/Atmel/AT91SAM9G10/SSC1/SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXRDY)TXRDY 0 (TXEMPTY)TXEMPTY 0 (ENDTX)ENDTX 0 (TXBUFE)TXBUFE 0 (RXRDY)RXRDY 0 (OVRUN)OVRUN 0 (ENDRX)ENDRX 0 (RXBUFF)RXBUFF 0 (CP0)CP0 0 (CP1)CP1 0 (TXSYN)TXSYN 0 (RXSYN)RXSYN 0 (TXEN)TXEN 0 (RXEN)RXEN

Description

Status Register

Fields

TXRDY

Transmit Ready
TXEMPTY

Transmit Empty
ENDTX

End of Transmission
TXBUFE

Transmit Buffer Empty
RXRDY

Receive Ready
OVRUN

Receive Overrun
ENDRX

End of Reception
RXBUFF

Receive Buffer Full
CP0

Compare 0
CP1

Compare 1
TXSYN

Transmit Sync
RXSYN

Receive Sync
TXEN

Transmit Enable
RXEN

Receive Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data