Atmel /ATSAM4SA16B /CMCC /TYPE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TYPE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AP)AP 0 (GCLK)GCLK 0 (RANDP)RANDP 0 (LRUP)LRUP 0 (RRP)RRP 0 (DMAPPED)WAYNUM 0 (LCKDOWN)LCKDOWN 0 (CSIZE_1KB)CSIZE0 (CLSIZE_1KB)CLSIZE

CLSIZE=CLSIZE_1KB, CSIZE=CSIZE_1KB, WAYNUM=DMAPPED

Description

Cache Controller Type Register

Fields

AP

Access Port Access Allowed

GCLK

Dynamic Clock Gating Supported

RANDP

Random Selection Policy Supported

LRUP

Least Recently Used Policy Supported

RRP

Random Selection Policy Supported

WAYNUM

Number of Ways

0 (DMAPPED): Direct Mapped Cache

1 (ARCH2WAY): 2-way set associative

2 (ARCH4WAY): 4-way set associative

3 (ARCH8WAY): 8-way set associative

LCKDOWN

Lockdown Supported

CSIZE

Data Cache Size

0 (CSIZE_1KB): Data cache size is 1 Kbyte

1 (CSIZE_2KB): Data cache size is 2 Kbytes

2 (CSIZE_4KB): Data cache size is 4 Kbytes

3 (CSIZE_8KB): Data cache size is 8 Kbytes

CLSIZE

Cache LIne Size

0 (CLSIZE_1KB): Cache line size is 4 bytes

1 (CLSIZE_2KB): Cache line size is 8 bytes

2 (CLSIZE_4KB): Cache line size is 16 bytes

3 (CLSIZE_8KB): Cache line size is 32 bytes

Links

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