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Atmel /ATSAM4SD16C /CMCC /SR

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Interpret as SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSTS)CSTS

Description

Cache Controller Status Register

Fields

CSTS

Cache Controller Status

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data