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Atmel /ATSAMA5D31 /UDPHS /TST

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Interpret as TST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NORMAL)SPEED_CFG 0 (TST_J)TST_J 0 (TST_K)TST_K 0 (TST_PKT)TST_PKT 0 (OPMODE2)OPMODE2

SPEED_CFG=NORMAL

Description

UDPHS Test Register

Fields

SPEED_CFG

Speed Configuration

0 (NORMAL): Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode

2 (HIGH_SPEED): Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose.

3 (FULL_SPEED): Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake.
TST_J

Test J Mode
TST_K

Test K Mode
TST_PKT

Test Packet Mode
OPMODE2

OpMode2

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data