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Atmel /ATSAMA5D33 /LCDC /BASEIDR

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Interpret as BASEIDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE 0 (OVR)OVR

Description

Base Layer Interrupt Disabled Register

Fields

DMA

End of DMA Transfer Interrupt Disable Register
DSCR

Descriptor Loaded Interrupt Disable Register
ADD

Head Descriptor Loaded Interrupt Disable Register
DONE

End of List Interrupt Disable Register
OVR

Overflow Interrupt Disable Register

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data