Atmel /ATSAMA5D33 /LCDC /LCDIDR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LCDIDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOFID)SOFID 0 (DISID)DISID 0 (DISPID)DISPID 0 (FIFOERRID)FIFOERRID 0 (BASEID)BASEID 0 (OVR1ID)OVR1ID 0 (OVR2ID)OVR2ID 0 (HEOID)HEOID 0 (HCRID)HCRID 0 (PPID)PPID

Description

LCD Controller Interrupt Disable Register

Fields

SOFID

Start of Frame Interrupt Disable Register

DISID

LCD Disable Interrupt Disable Register

DISPID

Power UP/Down Sequence Terminated Interrupt Disable Register

FIFOERRID

Output FIFO Error Interrupt Disable Register

BASEID

Base Layer Interrupt Disable Register

OVR1ID

Overlay 1 Interrupt Disable Register

OVR2ID

Overlay 2 Interrupt Disable Register

HEOID

High End Overlay Interrupt Disable Register

HCRID

Hardware Cursor Interrupt Disable Register

PPID

Post Processing Interrupt Disable Register

Links

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