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Atmel /ATSAMA5D33 /LCDC /OVR1ISR

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Interpret as OVR1ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE 0 (OVR)OVR

Description

Overlay 1 Interrupt Status Register

Fields

DMA

End of DMA Transfer
DSCR

DMA Descriptor Loaded
ADD

Head Descriptor Loaded
DONE

End of List Detected Register
OVR

Overflow Detected

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data