NDQS=ENABLED, NR=ROW_11, UNAL=UNSUPPORTED, DLL=RESET_DISABLED, ZQ=INIT, DQMS=NOT_SHARED, ENRDM=OFF, NC=COL_9, NB=4
MPDDRC Configuration Register
| NC | Number of Column Bits. 0 (COL_9): 9 DDR column bits 1 (COL_10): 10 DDR column bits 2 (COL_11): 11 DDR column bits 3 (COL_12): 12 DDR column bits |
| NR | Number of Row Bits 0 (ROW_11): 11 row bits 1 (ROW_12): 12 row bits 2 (ROW_13): 13 row bits 3 (ROW_14): 14 row bits |
| CAS | CAS Latency 2 (DDR_CAS2): LPDDR1 CAS Latency 2 3 (DDR_CAS3): DDR2/LPDDR2/LPDDR1 CAS Latency 3 4 (DDR_CAS4): DDR2/LPDDR2 CAS Latency 4 5 (DDR_CAS5): DDR2/LPDDR2 CAS Latency 5 6 (DDR_CAS6): DDR2 CAS Latency 6 |
| DLL | Reset DLL 0 (RESET_DISABLED): Disable DLL reset. 1 (RESET_ENABLED): Enable DLL reset. |
| DIC_DS | Output Driver Impedance Control (Drive Strength) |
| DIS_DLL | DISABLE DLL |
| ZQ | ZQ Calibration 0 (INIT): Calibration command after initialization 1 (LONG): Long calibration 2 (SHORT): Short calibration 3 (RESET): ZQ Reset |
| OCD | Off-chip Driver |
| DQMS | Mask Data is Shared 0 (NOT_SHARED): DQM is not shared with another controller. 1 (SHARED): DQM is shared with another controller. |
| ENRDM | Enable Read Measure 0 (OFF): DQS/DDR_DATA phase error correction is disabled. 1 (ON): DQS/DDR_DATA phase error correction is enabled. |
| NB | Number of Banks. 0 (4): 4 banks 1 (8): 8 banks |
| NDQS | Not DQS: 0 (ENABLED): Not DQS is enabled. 1 (DISABLED): Not DQS is disabled. |
| DECOD | Type of Decoding |
| UNAL | Support Unaligned Access 0 (UNSUPPORTED): Unaligned access is not supported. 1 (SUPPORTED): Unaligned access is supported. |