TIMEOUT=0, LPCB=DISABLED, APDE=FAST, UPD_MR=DISABLED, CLK_FR=DISABLED, LPDDR2_PWOFF=DISABLED
MPDDRC Low-power Register
| LPCB | Low-power Command Bit 0 (DISABLED): Low-power Feature is inhibited. No power-down, self refresh and deep-power modes are issued to the DDR-SDRAM device. 1 (SELFREFRESH): The MPDDRC issues a Self Refresh command to the DDR-SDRAM device, the clock(s) is/are de-activated and the CKE signal is set low. The DDR-SDRAM device leaves the self refresh mode when accessed and reenters it after the access. 2 (POWERDOWN): The MPDDRC issues a Power-down Command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. 3 (DEEP_PWD): The MPDDRC issues a Deep Power-down command to the Low-power DDR-SDRAM device. |
| CLK_FR | Clock Frozen Command Bit 0 (DISABLED): Clock(s) is/are not frozen. 1 (ENABLED): Clock(s) is/are frozen. |
| LPDDR2_PWOFF | LPDDR2 Power Off Bit 0 (DISABLED): No power off sequence applied to LPDDR2. 1 (ENABLED): A power off sequence is applied to the LPDDR2 device. CKE is forced low. |
| PASR | Partial Array Self Refresh |
| DS | Drive Strength |
| TIMEOUT | Enter Low-power Mode 0 (0): The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. 1 (64): The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. 2 (128): The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. |
| APDE | Active Power Down Exit Time 0 (FAST): Fast Exit. 1 (SLOW): Low Exit. |
| UPD_MR | Update Load Mode Register and Extended Mode Register 0 (DISABLED): Update is disabled. |