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Atmel /ATSAMA5D33 /UDPHS /EPTSTA8

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Interpret as EPTSTA8

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FRCESTALL)FRCESTALL 0 (DATA0)TOGGLESQ_STA 0 (ERR_OVFLW)ERR_OVFLW 0 (RXRDY_TXKL)RXRDY_TXKL 0 (TX_COMPLT)TX_COMPLT 0 (TXRDY)TXRDY 0 (RX_SETUP)RX_SETUP 0 (STALL_SNT)STALL_SNT 0 (NAK_IN)NAK_IN 0 (NAK_OUT)NAK_OUT 0CURBK_CTLDIR 0 (1BUSYBANK)BUSY_BANK_STA 0BYTE_COUNT0 (SHRT_PCKT)SHRT_PCKT

BUSY_BANK_STA=1BUSYBANK, TOGGLESQ_STA=DATA0

Description

UDPHS Endpoint Status Register (endpoint = 8)

Fields

FRCESTALL

Stall Handshake Request
TOGGLESQ_STA

Toggle Sequencing

0 (DATA0): DATA0

1 (DATA1): DATA1

2 (DATA2): Reserved for High Bandwidth Isochronous Endpoint

3 (MDATA): Reserved for High Bandwidth Isochronous Endpoint
ERR_OVFLW

Overflow Error
RXRDY_TXKL

Received OUT Data/KILL Bank
TX_COMPLT

Transmitted IN Data Complete
TXRDY

TX Packet Ready
RX_SETUP

Received SETUP
STALL_SNT

Stall Sent
NAK_IN

NAK IN
NAK_OUT

NAK OUT
CURBK_CTLDIR

Current Bank/Control Direction
BUSY_BANK_STA

Busy Bank Number

0 (1BUSYBANK): 1 busy bank

1 (2BUSYBANKS): 2 busy banks

2 (3BUSYBANKS): 3 busy banks
BYTE_COUNT

UDPHS Byte Count
SHRT_PCKT

Short Packet

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data