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Atmel /ATSAMA5D34 /CAN1 /TCR

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Interpret as TCR

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https://regviz.com/r/Atmel/AT91SAM9X25/CAN1/TCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MB0)MB0 0 (MB1)MB1 0 (MB2)MB2 0 (MB3)MB3 0 (MB4)MB4 0 (MB5)MB5 0 (MB6)MB6 0 (MB7)MB7 0 (TIMRST)TIMRST

Description

Transfer Command Register

Fields

MB0

Transfer Request for Mailbox 0
MB1

Transfer Request for Mailbox 1
MB2

Transfer Request for Mailbox 2
MB3

Transfer Request for Mailbox 3
MB4

Transfer Request for Mailbox 4
MB5

Transfer Request for Mailbox 5
MB6

Transfer Request for Mailbox 6
MB7

Transfer Request for Mailbox 7
TIMRST

Timer Reset

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data