Regviz

Atmel /ATSAMA5D34 /DMAC0 /CTRLA2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRLA2

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Atmel/ATSAMA5D31/DMAC1/CTRLA2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BTSIZE0 (CHK_1)SCSIZE 0 (CHK_1)DCSIZE 0 (BYTE)SRC_WIDTH 0 (BYTE)DST_WIDTH 0 (DONE)DONE

DCSIZE=CHK_1, SCSIZE=CHK_1, DST_WIDTH=BYTE, SRC_WIDTH=BYTE

Description

DMAC Channel Control A Register (ch_num = 2)

Fields

BTSIZE

Buffer Transfer Size
SCSIZE

Source Chunk Transfer Size.

0 (CHK_1): 1 data transferred

1 (CHK_4): 4 data transferred

2 (CHK_8): 8 data transferred

3 (CHK_16): 16 data transferred
DCSIZE

Destination Chunk Transfer Size

0 (CHK_1): 1 data transferred

1 (CHK_4): 4 data transferred

2 (CHK_8): 8 data transferred

3 (CHK_16): 16 data transferred
SRC_WIDTH

Transfer Width for the Source

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width

3 (DWORD): the transfer size is set to 64-bit width
DST_WIDTH

Transfer Width for the Destination

0 (BYTE): the transfer size is set to 8-bit width

1 (HALF_WORD): the transfer size is set to 16-bit width

2 (WORD): the transfer size is set to 32-bit width

3 (DWORD): the transfer size is set to 64-bit width
DONE

Current Descriptor Stop Command and Transfer Completed Memory Indicator

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data