Atmel /ATSAMA5D34 /DMAC1 /DSCR5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSCR5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AHB_IF0)DSCR_IF 0DSCR

DSCR_IF=AHB_IF0

Description

DMAC Channel Descriptor Address Register (ch_num = 5)

Fields

DSCR_IF

Descriptor Interface Selection

0 (AHB_IF0): The buffer transfer descriptor is fetched via AHB-Lite Interface 0

1 (AHB_IF1): The buffer transfer descriptor is fetched via AHB-Lite Interface 1

2 (AHB_IF2): The buffer transfer descriptor is fetched via AHB-Lite Interface 2

DSCR

Buffer Transfer Descriptor Address

Links

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