Atmel /ATSAMA5D34 /LCDC /HEOISR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HEOISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA)DMA 0 (DSCR)DSCR 0 (ADD)ADD 0 (DONE)DONE 0 (OVR)OVR 0 (UDMA)UDMA 0 (UDSCR)UDSCR 0 (UADD)UADD 0 (UDONE)UDONE 0 (UOVR)UOVR 0 (VDMA)VDMA 0 (VDSCR)VDSCR 0 (VADD)VADD 0 (VDONE)VDONE 0 (VOVR)VOVR

Description

High-End Overlay Interrupt Status Register

Fields

DMA

End of DMA Transfer

DSCR

DMA Descriptor Loaded

ADD

Head Descriptor Loaded

DONE

End of List Detected

OVR

Overflow Detected

UDMA

End of DMA Transfer for U component

UDSCR

DMA Descriptor Loaded for U component

UADD

Head Descriptor Loaded for U component

UDONE

End of List Detected for U component

UOVR

Overflow Detected for U component

VDMA

End of DMA Transfer for V component

VDSCR

DMA Descriptor Loaded for V component

VADD

Head Descriptor Loaded for V component

VDONE

End of List Detected for V component

VOVR

Overflow Detected for V component

Links

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