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Atmel /ATSAMA5D34 /LCDC /PPCFG0

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Interpret as PPCFG0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SIF)SIF 0 (AHB_BLEN_SINGLE)BLEN 0 (DLBO)DLBO

BLEN=AHB_BLEN_SINGLE

Description

Post Processing Configuration Register 0

Fields

SIF

Source Interface
BLEN

AHB Burst Length

0 (AHB_BLEN_SINGLE): AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats.

1 (AHB_BLEN_INCR4): AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats.

2 (AHB_BLEN_INCR8): AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats.

3 (AHB_BLEN_INCR16): AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats.
DLBO

Defined Length Burst Only For Channel Bus Transaction.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data