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Atmel /ATSAMA5D34 /USART0 /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RSTRX)RSTRX 0 (RSTTX)RSTTX 0 (RXEN)RXEN 0 (RXDIS)RXDIS 0 (TXEN)TXEN 0 (TXDIS)TXDIS 0 (RSTSTA)RSTSTA 0 (STTBRK)STTBRK 0 (STPBRK)STPBRK 0 (STTTO)STTTO 0 (SENDA)SENDA 0 (RSTIT)RSTIT 0 (RSTNACK)RSTNACK 0 (RETTO)RETTO 0 (RTSEN)RTSEN 0 (RTSDIS)RTSDIS

Description

Control Register

Fields

RSTRX

Reset Receiver
RSTTX

Reset Transmitter
RXEN

Receiver Enable
RXDIS

Receiver Disable
TXEN

Transmitter Enable
TXDIS

Transmitter Disable
RSTSTA

Reset Status Bits
STTBRK

Start Break
STPBRK

Stop Break
STTTO

Start Time-out
SENDA

Send Address
RSTIT

Reset Iterations
RSTNACK

Reset Non Acknowledge
RETTO

Rearm Time-out
RTSEN

Request to Send Enable
RTSDIS

Request to Send Disable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data