DMA Request Selection Register
| ADCSCAN0 | The scan conversion interrupt signal of the A/D converter unit 0 is output as a transfer request to the DMAC. |
| ADCSCAN1 | The scan conversion interrupt signal of the A/D converter unit 1 is output as a transfer request to the DMAC. |
| ADCSCAN2 | The scan conversion interrupt signal of the A/D converter unit 2 is output as a transfer request to the DMAC. |
| IRQ0BT0 | The IRQ0 interrupt signal of the base timer ch.0 is output as a transfer request to the DMAC. |
| IRQ0BT2 | The IRQ0 interrupt signal of the base timer ch.3 is output as a transfer request to the DMAC. |
| IRQ0BT4 | The IRQ0 interrupt signal of the base timer ch.4 is output as a transfer request to the DMAC. |
| IRQ0BT6 | The IRQ0 interrupt signal of the base timer ch.6 is output as a transfer request to the DMAC. |
| MFS0RX | The reception interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). |
| MFS0TX | The transmission interrupt signal of the MFS ch.0 is output as a transfer request to the DMAC (including extension). |
| MFS1RX | The reception interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). |
| MFS1TX | The transmission interrupt signal of the MFS ch.1 is output as a transfer request to the DMAC (including extension). |
| MFS2RX | The reception interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). |
| MFS2TX | The transmission interrupt signal of the MFS ch.2 is output as a transfer request to the DMAC (including extension). |
| MFS3RX | The reception interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). |
| MFS3TX | The transmission interrupt signal of the MFS ch.3 is output as a transfer request to the DMAC (including extension). |
| MFS4RX | The reception interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). |
| MFS4TX | The transmission interrupt signal of the MFS ch.4 is output as a transfer request to the DMAC (including extension). |
| MFS5RX | The reception interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). |
| MFS5TX | The transmission interrupt signal of the MFS ch.5 is output as a transfer request to the DMAC (including extension). |
| MFS6RX | The reception interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). |
| MFS6TX | The transmission interrupt signal of the MFS ch.6 is output as a transfer request to the DMAC (including extension). |
| MFS7RX | The reception interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). |
| MFS7TX | The transmission interrupt signal of the MFS ch.7 is output as a transfer request to the DMAC (including extension). |
| EXINT0 | The interrupt signal of the external interrupt ch.0 is output as a transfer request to the DMAC (including extension). |
| EXINT1 | The interrupt signal of the external interrupt ch.1 is output as a transfer request to the DMAC (including extension). |
| EXINT2 | The interrupt signal of the external interrupt ch.2 is output as a transfer request to the DMAC (including extension). |
| EXINT3 | The interrupt signal of the external interrupt ch.3 is output as a transfer request to the DMAC (including extension). |