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Fujitsu /MB9AF14xM /CRTRIM /MCR_RLR

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Interpret as MCR_RLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRMLCK

Description

High-Speed CR Oscillation Register Write-Protect Register

Fields

TRMLCK

Register write-protect bits

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data