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Fujitsu /MB9AF15xM /EXBUS /DCLKR

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Interpret as DCLKR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MDIV0 (MCLKON)MCLKON

Description

Division Clock Register

Fields

MDIV

MCLK Division Ratio Setup
MCLKON

MCLK ON

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data