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Fujitsu /MB9AF1AxL /BT0 /PWC_TMCR

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Interpret as PWC_TMCR

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CTEN)CTEN 0 (MDSE)MDSE 0FMD0 (T32)T32 0EGS0CKS2_0

Description

Timer Control Register

Fields

CTEN

Timer enable bit
MDSE

Mode selection bit
FMD

Timer function selection bits
T32

32-bit timer selection bit
EGS

Measurement edge selection bits
CKS2_0

Count clock selection bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data