Fujitsu /MB9AF1AxM /CRG /PSW_TMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PSW_TMR

7 43 0 0 00 0 0 0 0 0 0 0 0POWT0 (PINC)PINC

Description

PLL Clock Stabilization Wait Time Setup Register

Fields

POWT

PLL clock stabilization wait time setup bit

PINC

PLL input clock select bit

Links

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