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Fujitsu /MB9AFA3xL /LCDC /LCDCC1

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Interpret as LCDCC1

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7 43 0 0 00 0 0 0 0 0 0 0 0MS0 (VSEL)VSEL 0 (LCDEN)LCDEN

Description

LCDC Control Register 1

Fields

MS

LCD controller display mode selection bits
VSEL

LCD drive power control bit
LCDEN

Timer mode operation enable bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data