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Fujitsu /MB9AFB4xL /GPIO /DDR0

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Interpret as DDR0

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https://regviz.com/r/Fujitsu/MB9AF11xL/GPIO/DDR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P0)P0 0 (P1)P1 0 (P2)P2 0 (P3)P3 0 (P4)P4 0 (PA)PA 0 (PB)PB 0 (PC)PC 0 (PD)PD 0 (PE)PE 0 (PF)PF

Description

Port input/output direction setting register 0

Fields

P0

Bit0 of DDR0
P1

Bit1 of DDR0
P2

Bit2 of DDR0
P3

Bit3 of DDR0
P4

Bit4 of DDR0
PA

Bit10 of DDR0
PB

Bit11 of DDR0
PC

Bit12 of DDR0
PD

Bit13 of DDR0
PE

Bit14 of DDR0
PF

Bit15 of DDR0

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data