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Fujitsu /MB9B160R /DMAC /DMACR

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Interpret as DMACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DH0 (PR)PR 0 (DS)DS 0 (DE)DE

Description

Entire DMAC Configuration Register

Fields

DH

DMA Halt (All-channel pause bit)
PR

Priority Rotation
DS

DMA Stop
DE

DMA Enable (all-channel operation enable bit)

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data