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Fujitsu /MB9BF11xN /CRG /APBC2_PSR

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Interpret as APBC2_PSR

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7 43 0 0 00 0 0 0 0 0 0 0 0APBC2 0 (APBC2RST)APBC2RST 0 (APBC2EN)APBC2EN

Description

APB2 Prescaler Register

Fields

APBC2

APB2 bus clock frequency division ratio setting bit
APBC2RST

APB2 bus reset control bit
APBC2EN

APB2 clock enable bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data