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Fujitsu /MB9BF12xS /GPIO /DDR0

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Interpret as DDR0

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https://regviz.com/r/Fujitsu/MB9BF42xS/GPIO/DDR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P0)P0 0 (P1)P1 0 (P2)P2 0 (P3)P3 0 (P4)P4 0 (P5)P5 0 (P6)P6 0 (P7)P7 0 (P8)P8 0 (P9)P9

Description

Port input/output direction setting register 0

Fields

P0

Bit0 of DDR0
P1

Bit1 of DDR0
P2

Bit2 of DDR0
P3

Bit3 of DDR0
P4

Bit4 of DDR0
P5

Bit5 of DDR0
P6

Bit6 of DDR0
P7

Bit7 of DDR0
P8

Bit8 of DDR0
P9

Bit9 of DDR0

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data