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Fujitsu /MB9BF31xT /GPIO /DDR0

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Interpret as DDR0

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https://regviz.com/r/Spansion/MB9BF31xN/GPIO/DDR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (P00)P00 0 (P01)P01 0 (P02)P02 0 (P03)P03 0 (P04)P04 0 (P05)P05 0 (P06)P06 0 (P07)P07 0 (P08)P08 0 (P09)P09 0 (P0A)P0A 0 (P0B)P0B 0 (P0C)P0C 0 (P0D)P0D 0 (P0E)P0E 0 (P0F)P0F

Description

Port input/output direction setting register 0

Fields

P00

Bit0 of DDR0
P01

Bit1 of DDR0
P02

Bit2 of DDR0
P03

Bit3 of DDR0
P04

Bit4 of DDR0
P05

Bit5 of DDR0
P06

Bit6 of DDR0
P07

Bit7 of DDR0
P08

Bit8 of DDR0
P09

Bit9 of DDR0
P0A

Bit10 of DDR0
P0B

Bit11 of DDR0
P0C

Bit12 of DDR0
P0D

Bit13 of DDR0
P0E

Bit14 of DDR0
P0F

Bit15 of DDR0

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data