Fujitsu /MB9BF40xR /DMAC /DMACA0

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Interpret as DMACA0

31282724232019161512118743000000000000000000000000000000000000000000TC0BC0IS0 (ST)ST0 (PB)PB0 (EB)EB

Description

Configuration A Register

Fields

TC

Transfer Count

BC

Block Count

IS

Input Select

ST

Software Trigger

PB

Pause bit (individual-channel pause bit)

EB

Enable bit (individual-channel operation enable bit)

Links

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