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Fujitsu /MB9BF41xS /WC /CLK_SEL

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Interpret as CLK_SEL

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SEL_IN)SEL_IN 0 (SEL_OUT)SEL_OUT

Description

Clock Selection Register

Fields

SEL_IN

Input clock selection bit
SEL_OUT

Output clock selection bit

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data