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Fujitsu /MB9BF51xS /DMAC /DMACA0

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Interpret as DMACA0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TC0BC0IS0 (ST)ST 0 (PB)PB 0 (EB)EB

Description

Configuration A Register

Fields

TC

Transfer Count
BC

Block Count
IS

Input Select
ST

Software Trigger
PB

Pause bit (individual-channel pause bit)
EB

Enable bit (individual-channel operation enable bit)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data